1. Field of the Invention
The present invention generally relates to a semiconductor device having a semiconductor chip on which interconnections are formed and a method of manufacturing the semiconductor device.
2. Description of the Related Art
Examples of products using semiconductors are recently used for various mobile apparatuses such as digital cameras and portable phones, and are rapidly becoming small-sized, thinned, and trimmed weight. The small-size and high-density are required also in semiconductor devices such as a NAND flash memory. So-called chip size package (CSP) which has substantially the same size as a semiconductor chip in the plan view as illustrated in FIG. 1 has been proposed as illustrated in FIG. 1. It is also required to reduce the price in addition to decreasing the small size and increasing the high density.
Hereinafter, examples of a semiconductor device and a manufacturing method of the semiconductor device are described. FIG. 1 is a cross-sectional view of the above example of the semiconductor device. Referring to FIG. 1, the semiconductor device 100 includes a semiconductor chip 101, an internal connection terminal 102, an insulating layer 103, an interconnection 104, a solder resist 106, and an externally connecting pad 107.
The semiconductor chip 101 includes a semiconductor substrate 109, a semiconductor element 111, an electrode pad 112, and a protection film 113. The semiconductor substrate 109 is obtained by taking apart a thinned Si wafer into pieces.
The semiconductor integrated circuit 111 is provided on a surface side of the semiconductor substrate 109. The semiconductor integrated circuit 111 is made of a diffusion layer, an insulating layer, via holes, interconnections or the like (not illustrated). Plural electrode pads 112 are provided on the semiconductor integrated circuits 111. The plural electrode pads 112 are electrically connected to the interconnections provided on the semiconductor integrated circuit 111. The protection layer 113 is provided on the semiconductor integrated circuit 111. The protection layer 113 is a film for protecting the semiconductor integrated circuit 111.
The internal connection terminal 102 is provided on the electrode pad 112. The upper end portions of the internal connection terminals 102 are exposed from the insulating layer 103. The upper end portions of the internal connection terminals 102 are connected to the interconnections 104. The insulating layer 103 is provided to cover the semiconductor chip 101 on a side where the internal connection terminal 102 is provided. The insulating layer 103 is a sheet-like insulating resin having adhesiveness such as a non conductive film (NCF). Such a sheet-like insulating resin may ordinarily be epoxy resin or cyanate ester series resin which has opalescent or colorless transparency. Alpha rays, visible rays, and ultraviolet rays transmit through the insulating layer 103 to a semiconductor integrated circuit 111 positioned below the insulating layer 103.
The interconnections 104 are provided on the insulating layer 103. The interconnections 104 are connected to the internal connection terminal 102. The interconnections 104 are electrically connected to the electrode pads 112 via the internal connection terminals 102. The interconnection 104 has a region for externally connecting pad 104A in which the externally connecting pad 107 is provided. The solder resist 106 is formed on the insulating layer 103 to cover the interconnections 104 except for the region for externally connecting pad 104A.
The externally connecting pads 107 are provided on the regions for externally connecting pad 104A of the interconnections 104. The externally connecting pads 107 are connected to the interconnections 104. The material of the externally connecting pads 107 may be an alloy containing Pb, an alloy containing Sn and Cu, an alloy containing Sn and Ag, an alloy containing Sn, Ag, and Cu, or the like.
FIG. 2 is a plan view of a semiconductor substrate on which the example semiconductor device of FIG. 1 is formed. Referring to FIG. 2, reference symbol 110 designates a semiconductor substrate, and reference symbol C designates positions (hereinafter, referred to as cutting position C) where the semiconductor substrate 110 is cut. Referring to FIG. 2, the semiconductor substrate 110 includes plural semiconductor device forming regions A and scribe regions B for separating the plural semiconductor device forming regions A. The semiconductor devices 100 are formed on the plural semiconductor device forming regions A. The semiconductor substrate 110 becomes the semiconductor substrate 109 (see FIG. 1) described above by thinning the semiconductor substrate 110 and cutting the thinned semiconductor substrate 110 at cutting positions C.
FIG. 3 thru FIG. 11 illustrate manufacturing processes of the example semiconductor device illustrated in FIG. 1. Referring to FIG. 3 to FIG. 11, the same reference symbols are attached to portions which are the same as those of the semiconductor device 100 illustrated in FIG. 1, and description of these portions may be omitted. Referring to FIG. 3 to FIG. 11, reference symbol A designates the plural semiconductor device forming regions (hereinafter, referred to as semiconductor device forming region A), reference symbol B designates the scribe regions (hereinafter, referred to as scribe region B), and reference symbol C designates the cutting positions (hereinafter, referred to as cutting position C) where the semiconductor substrate 110 is cut by the dicing blade.
First, in the process illustrated in FIG. 3, the semiconductor chip 101 having the semiconductor integrated circuit 111, plural electrode pads 112, and the protection layer 113 is formed on a surface side of the semiconductor substrate 110 before the semiconductor substrate 110 is thinned. Next, in the process of FIG. 4, the internal connection terminals 102 are formed in plural electrode pads 112. At this stage, there are variations of heights in the internal connection terminals 102.
In the process illustrated in FIG. 5, a flat plate 115 is pressured on the internal connection terminals 102 to arrange the heights of the plural internal connection terminals 102 to level the heights. In the process illustrated in FIG. 6, the insulating layer 103 made of the resin is formed to cover the semiconductor chip 101 on the side of forming the internal connection terminal 102 and the internal connection terminal 102. As described, the insulating layer 103 may be the sheet-like insulating resin having adhesiveness such as a non conductive film (NCF). As described, such a sheet-like insulating resin may ordinarily be epoxy resin or cyanate ester series resin which has opalescent or colorless transparency. Alpha rays, visible rays, and ultraviolet rays transmit through the insulating layer 103 to a semiconductor integrated circuit 111 positioned below the insulating layer 103.
In the process illustrated in FIG. 7, the insulating layer 103 is polished until upper surfaces 102A of the internal connection terminals 102 are exposed from the insulating layer 103. The insulating layer 103 is polished so that the upper surface 103A of the insulating layer 103 becomes substantially the same as the upper surface 102A of the internal connection terminal 102. With this, the upper surface of the structural body, specifically the upper surface 103A of the insulating layer 103 and the upper surfaces 102 of the internal connection terminals 102 illustrated in FIG. 7, becomes flat.
Referring to FIG. 8, the interconnection 104 is formed on the flattened upper surface of the structural body illustrated in FIG. 7. Specifically, the interconnections 104 may be formed by attaching a metallic foil (not illustrated) to the structural body, coating a resist on the metallic foil to cover the metallic foil, and exposing the resist to light and developing to form a resist film (not illustrated) on the metallic foil at a portion corresponding to forming regions for the interconnections 104. Thereafter, the metallic foil is etched using the resist film as a mask to form the interconnection 104 as a subtractive method. Thereafter, the resist film is removed.
In the process illustrated in FIG. 9, the solder resist 106 is formed on the insulating layer 103 to cover the interconnections 104 other than the regions 104A for externally connecting pads 107. In the process illustrated in FIG. 10, the semiconductor substrate 110 is polished from the back side of the semiconductor substrate 110 to thin the semiconductor substrate 110. In the process illustrated in FIG. 11, the externally connecting pads 107 are formed on the regions for externally connecting pad 104A. The material of the externally connecting pads 107 may be an alloy containing Pb, an alloy containing Sn and Cu, an alloy containing Sn and Ag, an alloy containing Sn, Ag, and Cu, or the like. Thereafter, by cutting the semiconductor substrate 110 at a portion corresponding to the cutting position C, plural semiconductor devices 100 can be manufactured.
In the above manufacturing processes, inferior semiconductor chips may be packaged. When the inferior semiconductor chips are packaged, there occurs a drop of yield in the semiconductor chips, the manufacturing cost increases, and the price reduction cannot be realized. One reason why the semiconductor chips manufactured are inferior may be peeling-off of the insulating layer from the semiconductor chip 101. This peeling-off of the insulating layer 103 is caused by insufficient adhesiveness contact between the protection layer 113 of the semiconductor chip 101 and the insulating layer 103 formed on the protection layer 113. This peeling-off has been a problem.    [Patent Document 1] Japanese Patent No. 3313547    [Patent Document 2] Japanese Patent No. 3614828    [Patent Document 3] Japanese Patent No. 3614829